SH7708 Datasheet, PDF (100/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

the next instruction after a delayed unconditional branch instruction, or the next instruction when a
delayed conditional branch instruction is true.
4 . 2 . 4 Exception Codes
Table 4.3 lists the exception codes written to bits 11–0 of the EXPEVT register (for reset or
general exceptions) or the INTEVT register (for general interrupt requests) to identify each specific
exception event. An additional exception register, the TRAPA (TRA) register, is used to hold the
8-bit immediate data in an unconditional trap (TRAPA instruction).
Table 4.3 Exception Codes
Exception Type
Reset
General exception events
General interrupt requests
86
Exception Event
Power-on
Manual reset
TLB miss/invalid (load)
TLB miss/invalid (store)
Initial page write
TLB protection violation (load)
TLB protection violation (store)
Address error (load)
Address error (store)
Unconditional trap (TRAPA instruction)
Reserved instruction code exception
Illegal slot instruction exception
User break point trap
Nonmaskable interrupt
External hardware interrupts:
IRL3–IRL0 = 0000
IRL3–IRL0 = 0001
IRL3–IRL0 = 0010
IRL3–IRL0 = 0011
IRL3–IRL0 = 0100
IRL3–IRL0 = 0101
IRL3–IRL0 = 0110
IRL3–IRL0 = 0111
IRL3–IRL0 = 1000
Exception
Code
H'000
H'020
H'040
H'060
H'080
H'0A0
H'0C0
H'0E0
H'100
H'160
H'180
H'1A0
H'1E0
H'1C0
H'200
H'220
H'240
H'260
H'280
H'2A0
H'2C0
H'2E0
H'300