SH7708 Datasheet, PDF (237/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

10.2.11 Refresh Time Constant Register (RTCOR)
The refresh time constant register (RTCOR) is a 16-bit read/write register. The values of RTCOR
and RTCNT (lower 8 bits) are constantly compared. When the values match, the compare match
flag (CMF) in RTCSR is set and RTCNT is cleared to 0. When the refresh bit (RFSH) in the
individual memory control register (MCR) is set to 1 and the refresh mode is set to CAS-before-
RAS refresh, a memory refresh cycle occurs when the CMF bit is set. RTCOR is initialized to
H'00 by a power-on reset. It is not initialized by a manual reset or in standby mode, but retains its
contents.
Note:
The method for writing to RTCOR is different from that for general registers to prevent
inadvertent overwriting. Using a word transfer instruction, place B'10100101 in the upper
byte and the write data in the lower byte. For details, see section 10.2.13, Cautions on
Accessing Refresh Control Related Registers.
Bit: 15
14
13
12
11
10
9
8
Bit name: —
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
Bit name:
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
10.2.12 Refresh Count Register (RFCR)
The refresh count register (RFCR) is a 16-bit read/write register containing a 10-bit counter that
increments every time RTCOR and RTCNT match. When RFCR exceeds the count limit value set
by the LMTS bit in RTCSR, the OVF bit in RTCSR is set and RFCR is cleared. RFCR is
initialized to H'0000 by a power-on reset. It is not initialized by a manual reset or in standby
mode, but retains its contents.
Note:
The method for writing to RFCR is different from that for general registers to prevent
inadvertent overwriting. Using a word transfer instruction, place B'101001 in the top 6 bits
of the upper byte, and the write data in the remaining bits. For details, see section 10.2.13,
Cautions on Accessing Refresh Control Related Registers.
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