SH7708 Datasheet, PDF (447/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 16.7 Clock Timing (V_CC = 3.3 ± 0.3 V, Ta = –20 to 75°C, Maximum External
Bus Operating Frequency: 60 MHz) (cont)
Item
PLL synchronization settling time
Symbol Min
t_PLL
100
IRL interrupt decision time (using RTC and t_IRLSTB 100
in standby mode)
Notes: 1. PLL circuit 2 in operation.
2. IPLL circuit 2 not in operation.
Max
—
—
Unit
µs
µs
Figure
16.8,
16.9,
16.10
16.10
EXTAL*
(input)
1/2 V_CC
t_EXH
t_EXcyc
t_EXL
V_IH
V_IH
V_IL
V_IL
t_EXF
V_IH
1/2 V_CC
t_EXR
Note: The clock input from the EXTAL pin.
Figure 16.1 EXTAL Clock Input Timing
CKIO
(input)
1/2 V_CC
tCKI_cyc
t_CKIH
t_CKIL
V_IH
V_IH
V_IL
V_IH
V_IL
1/2 V_CC
t_CKIF
t_CKIR
Figure 16.2 CKIO Clock Input Timing
433