SH7708 Datasheet, PDF (569/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table A.2 Pin Specifications (cont)
Pin
Pin No.
D15 to D0
15 to 16,
21 to 29,
32 to 36
CS6/CE1B
108
CS5/CE1A
109
CS4 to CS0
110 to 114
BS
105
RAS/CE
129
CASHH/CAS2H 119
CASHL /CAS2L 120
CASLH
125
CASLL/CAS/OE 126
WE3 /DQMUU/ 117
ICIOWR
WE2/DQMUL/ 118
ICIORD
WE1 /DQMLU 123
WE0 /DQMLL 124
RD/WR
106
RD
107
WAIT
132
IOIS16
94
BREQ
87
BACK
96
IRQOUT
95
RESET
88
CA
81
I / O Function
I/O Data bus
O
Chip select 6/PCMCIA CE
O
Chip select 5/PCMCIA CE
O
Chip select 4—chip select 0
O
Bus cycle start
O
DRAM, synchronous DRAM RAS/pseudo-SRAM CE
O
D31–D24 (DRAM CAS)/D15–D8 (area 2 DRAM CAS)
select signal
O
D23-D16 (DRAM CAS)/D7–D0 (area 2 DRAM CAS) select
signal
O
D15–D8 select signal (DRAM CAS)
O
D7–D0 select (DRAM CAS)/memory select signal
(synchronous DRAM CAS/pseudo-SRAM OE)
O
D31–D24 select signal (normal memory, pseudo-SRAM
WE /synchronous DRAM DQM)/IO write (PCMCIA,
PCMCIB)
O
D23–D16 select signal (normal memory, pseudo-SRAM
WE /synchronous DRAM DQM)/IO write (PCMCIA,
PCMCIB)
O
D15–D8 select signal (normal memory, pseudo-SRAM
WE/synchronous DRAM DQM)
O
D7–D0 select signal (normal memory, pseudo-SRAM
WE/synchronous DRAM DQM)
O
Read/write (synchronous DRAM/DRAM/PCMCIA)
O
Read pulse (PCMCIA/normal memory)
I
Hardware wait request
I
IO16 bit indication (PCMCIA IO area)
I
Bus request
O
Bus acknowledge
O
Interrupt request notification
I
Reset
I
Chip active
Causes a transition to hardware standby mode when
low. Drive high in a power-on reset.
555