SH7708 Datasheet, PDF (192/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 9.5 Register Configuration
Name
Abbreviatio R/W Size
n
Initial
Value
Address
Watchdog timer counter WTCNT
R/W* R: byte;
W: word*
H'00
H'FFFFFF84
Watchdog timer
control/status register
WTCSR
R/W* R: byte;
W: word*
H'00
H'FFFFFF86
Note: Write with a word access. Write H'5A and H'A5, respectively, in the upper bytes. Byte or
longword writes are not possible. Read with a byte access.
9 . 9 WDT Registers
9 . 9 . 1 Watchdog Timer Counter (WTCNT)
The watchdog timer counter (WTCNT) is an 8-bit read/write counter that increments on the
selected clock. When an overflow occurs, it generates a reset in watchdog timer mode and an
interrupt in interval time mode. Its address is H'FFFFFF84. The WTCNT counter is initialized to
H'00 only by a power-on reset through the RESET pin. Use a word access to write to the WTCNT
counter, with H'5A in the upper byte. Use a byte access to read WTCNT.
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
9 . 9 . 2 Watchdog Timer Control/Status Register (WTCSR)
The watchdog timer control/status register (WTCSR) is an 8-bit read/write register composed of
bits to select the clock used for the count, bits to select the timer mode, and overflow flags. Its
address is H'FFFFFF86. The WTCSR register is initialized to H'00 only by a power-on reset
through the RESET pin. When a WDT overflow causes an internal reset, the WTCSR retains its
value. When used to count the clock settling time for canceling a standby, it retains its value after
counter overflow. Use a word access to write to the WTCSR counter, with H'A5 in the upper byte.
Use a byte access to read WTCSR.
Bit:
Initial value:
R/W:
7
TME
0
R/W
6
WT/IT
0
R/W
5
RSTS
0
R/W
4
WOVF
0
R/W
3
IOVF
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
178