SH7708 Datasheet, PDF (119/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

is way 2, 11 is way 3 in normal mode; 00 and 10 are way 0, and 01 and 11 are way 1 in RAM
mode), and H'F1 to indicate data array access (bits 31–24).
Both reading and writing use the longword of the data array specified by the entry address, way
number and longword address. The access size of the data array is fixed at longword.
(1) Address array access
Address specification
Read access
31
24 23
13 12 11 10
432
0
* * ^11110000
––––
W
Entry
0_{* **}
Write access
31
24 23
13 12 11 10
11110000
* ^{––––} *
W
Data specification (both read and write accesses)
31
10
Address tag (31–10)
4
Entry
9
4
LRU
32
0
A _{* **}
3 21 0
XX
UV
(2) Data array access (both read and write accesses)
Address specification
31
24 23
13 12 11 10
11110001
* ^{––––} *
W
Entry
Data specification
31
Longword
43
21
0
L _**
0
X: 0 for read, don’t care bit for write
*^{: Don’t care bit}
Figure 5.5 Specifying Address and Data for Memory-Mapped Cache Access
105