SH7708 Datasheet, PDF (293/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

With pseudo-SRAM, self-refresh mode is entered by holding the RFSH signal low for at least the
prescribed time. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit to
1. The self-refresh state is maintained while the CKE signal is low. Pseudo-SRAM cannot be
accessed while in self-refresh state. Self-refresh mode is cleared by clearing the RMODE bit to 0.
After self-refresh mode has been cleared, access to pseudo-SRAM is disabled for the number of
cycles specified by the TPC bits in MCR, but if the refresh reset time needed to return from self-
refreshing is longer than this interval, coding must be provided to ensure that no access—including
auto-refresh—is made to pseudo-SRAM. Self-refresh timing is shown in figure 10.37. Settings
must be made so that self-refresh clearing and data retention is performed correctly after self-refresh
mode is cleared, and auto-refreshing is performed at the correct intervals. If the transition from
clearing of self-refresh mode to the start of auto-refreshing takes time, this time should be taken
into consideration when setting the initial value of RTCNT.
Self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in a manual
reset.
TRc TRr1
TSR TSR2 (Tpc) (Tpc)
CKIO
CE
(High)
OE/RFSH
Figure 10.37 Pseudo-SRAM Self-Refreshing
Power-On Sequence: After powering pseudo-SRAM on, a minimum wait time of 100 µs is
requested during which no access can be performed, followed by the prescribed number (usually 8
or more) of dummy auto-refresh cycles. As the bus state controller does not perform any special
operations for a power-on reset, the power-on sequence must be carried out by the initialization
program executed after a power-on reset.
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