SH7708 Datasheet, PDF (506/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

17.3.1 Clock Timing
Table 17.5 Clock Timing (V_CC = 3.15Å–3.6 V, Ta = –20 to 75°C, Maximum External
Bus Operating Frequency: 60 MHz)
Item
EXTAL clock input frequency
EXTAL clock input cycle time
EXTAL clock input low-level pulse width
EXTAL clock input high-level pulse width
EXTAL clock input rise time
EXTAL clock input fall time
CKIO clock frequency (input)
CKIO clock cycle time (input)
CKIO clock low-level pulse width (input)
CKIO clock high-level pulse width (input)
CKIO clock rise time (input)
CKIO clock fall time (input)
CKIO clock output frequency (output)
CKIO clock cycle time (output)
CKIO clock low-level pulse width (output)
CKIO clock high-level pulse width (output)
CKIO clock rise time (output)
CKIO clock fall time (output)
Power-on oscillation settling time
Power-on oscillation settling time/mode setting
BREQ reset hold time
RESET set-up time
BREQ set-up time
MD reset hold time
Reset assert time
Symbol
f _EX
tEXcyc
t _EXL
t _EXH
t _EXR
t _EXF
f _CKI
t _CKIcyc
t _CKIL
t _CKIH
t _CKIR
t _CKIF
f _OP
tcyc
t _CKOL
t _CKOH
t _CKOR
t _CKOF
t _OSC1
t _OSCMD
t _BREQRH
t _RESS
t _BREQS
t _MDRH
t _RESW
Min
5
16.7
4*1 or 10*2
4*1 or 10*2
—
—
16
16.7
4
4
—
—
16
16.7
3
3
—
—
10
10
0
20
20
20
20
Max
60
200
—
—
2
2
60
62.5
—
—
2
2
60
62.5
—
—
5
5
—
—
—
—
—
—
—
Standby return oscillation settling time 1
t _OSC2
10
—
Standby return oscillation settling time 2
t _OSC3
10
—
Standby return oscillation settling time 3
t _OSC4
11
—
PLL synchronization settling time
t _PLL
100
—
IRL interrupt decision time (using RTC and in
tIRLSTB 100
—
standby mode)
Notes: 1. PLL circuit 2 in operation.
492
Unit
MHz
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
tcyc
ms
ms
ms
µs
µs
Figure
17.1
17.2
17.3
17.4
17.4,
17.5,
17.11
17.5
17.6
17.7
17.8,
17.9,
17.10
17.10