SH7708 Datasheet, PDF (144/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

7 . 2 . 9 Break Data Register B (BDRB)
Bit:
Bit name:
Initial value:
R/W:
31
BDB31
—
R/W
30
BDB30
—
R/W
29
BDB29
—
R/W
28
BDB28
—
R/W
27
BDB27
—
R/W
26
BDB26
—
R/W
25
BDB25
—
R/W
24
BDB24
—
R/W
Bit:
Bit name:
Initial value:
R/W:
23
BDB23
—
R/W
22
BDB22
—
R/W
21
BDB21
—
R/W
20
BDB20
—
R/W
19
BDB19
—
R/W
18
BDB18
—
R/W
17
BDB17
—
R/W
16
BDB16
—
R/W
Bit: 15
Bit name: BDB15
Initial value: —
R/W: R/W
14
BDB14
—
R/W
13
BDB13
—
R/W
12
BDB12
—
R/W
11
BDB11
—
R/W
10
BDB10
—
R/W
9
BDB9
—
R/W
8
BDB8
—
R/W
Bit:
Bit name:
Initial value:
R/W:
7
BDB7
—
R/W
6
BDB6
—
R/W
5
BDB5
—
R/W
4
BDB4
—
R/W
3
BDB3
—
R/W
2
BDB2
—
R/W
1
BDB1
—
R/W
0
BDB0
—
R/W
Break data register B (BDRB) is a 32-bit read/write register that specifies the data that is the break
condition for channel B data breaks. BDRB is not initialized by a reset.
BDRB Bits 31 to 0—Break Data B31 to B0 (BDB31 to BDB0): These bits store the data that is the
break condition for break channel B.
When byte access has been specified by the SZB bit in the BBRB register, set the same byte data
in bits BDB15–BDB8 as has been set in bits BDB7–BDB0. Bits BDB31–BDB16 are ignored when
either byte or word access is specified. When the instruction fetch cycle is specified as a channel B
break condition, or when the data bus is not included in the conditions according to the DBEB bit
specification in BRCR (0), the BDRB value is ignored.
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