SH7708 Datasheet, PDF (357/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit 5: TE
0
1
Description
Transmitter disabled
value)
(Initial
The transmit data register empty bit (TDRE) in the serial status register
(SCSSR) is locked at 1.
Transmitter enabled
Serial transmission starts when the transmit data register empty (TDRE)
bit in the serial status register (SCSSR) is cleared to 0 after writing of
transmit data into SCTDR. Select the transmit format in SCSMR before
setting TE to 1.
Bit 4—Receive Enable (RE): Enables or disables the SCI serial receiver.
Bit 4: RE
0
1
Description
Receiver disabled
value)
(Initial
Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER,
ORER). These flags retain their previous values.
Receiver enabled
Serial reception starts when a start bit is detected in asynchronous
mode, or synchronous clock input is detected in synchronous mode.
Select the receive format in SCSMR before setting RE to 1.
Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The
MPIE setting is used only in asynchronous mode, and only if the multiprocessor mode bit (MP) in
the serial mode register (SCSMR) is set to 1 during reception. The MPIE setting is ignored in
synchronous mode or when the MP bit is cleared to0.
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