SH7708 Datasheet, PDF(206/625 Page) Renesas Technology Corp – SuperH™ RISC engine

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SH7708 Datasheet, PDF (206/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

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10.1.4 Register Configuration

The BSC has 11 registers (table 10.2). The synchronous DRAM also has a built-in synchronous

DRAM mode register. These registers control direct connection interfaces to memory, wait states,

refreshes, and PCMCIA devices.

Table 10.2Register Configuration

Name

Abbr.

R/W Initial

Value*2

Address Bus Width

Bus control register 1

BCR1 R/W H'0000

H'FFFFFF60 16

Bus control register 2

BCR2 R/W H'3FFC

H'FFFFFF62 16

Wait state control register 1

WCR1 R/W H'3FFF

H'FFFFFF64 16

Wait state control register 2

WCR2 R/W H'FFFF

H'FFFFFF66 16

Individual memory control register MCR

R/W H'0000

H'FFFFFF68 16

DRAM control register

DCR

R/W H'0000

H'FFFFFF6A 16

PCMCIA control register

PCR

R/W H'0000

H'FFFFFF6C 16

Refresh timer control/status register RTCSR R/W H'0000

H'FFFFFF6E 16

Refresh timer counter

RTCNT R/W H'0000

H'FFFFFF70 16

Refresh time constant register

RTCOR R/W H'0000

H'FFFFFF72 16

Refresh count register

RFCR R/W H'0000

H'FFFFFF74 16

SDRAM mode register, area 2

SDMR W â

H'FFFFD000â 8

H'FFFFDFFF

SDRAM mode register, area 3

â

H'FFFFE000â

H'FFFFEFFF

Notes: 1. For details see section 10.2.8, Synchronous DRAM Mode Register.

2. Initialized during a power-on reset.

192

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