SH7708 Datasheet, PDF (107/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

• Reserved instruction exception
 Conditions:
a. When undefined code not in a delay slot is decoded
Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S,
BF/S
Undefined instructions: H'Fxxx(SH7708, SH7708S), H'FxxF(SH7708R)
b. When a privileged instruction not in a delay slot is decoded in user mode
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR
with LDC/STC are not privileged instructions
 Operations: The PC and SR of the instruction that generated the exception are saved to the
SPC and SSR, respectively. H'180 is set in EXPEVT. The BL, MD, and RB bits in SR
are set to 1 and a branch occurs to PC = VBR + H'0100. When an undefined instruction
other than H'Fxxx is decoded, operation cannot be guaranteed.
• Illegal slot instruction
 Conditions:
a. When undefined code in a delay slot is decoded
Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S,
BF/S
Undefined instructions: H'Fxxx(SH7708, SH7708S), H'FxxF(SH7708R)
b. When an instruction that rewrites the PC in a delay slot is decoded
Instructions that rewrite the PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT,
BF, BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L, @Rm+, SR
c. When a privileged instruction in a delay slot is decoded in user mode
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR
with LDC/STC are not privileged instructions
 Operations: The PC of the previous delay branch instruction is saved to the SPC. SR of the
instruction that generated the exception is saved to SSR. H'1A0 is set in EXPEVT. The
BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100.
When an undefined instruction other than H'Fxxx is decoded, operation cannot be
guaranteed.
• User break point trap
 Conditions: When a break condition set in the user break point controller is satisfied
 Operations: When a post-execution break occurs, the PC of the instruction immediately
after the instruction that set the break point is set in the SPC. If a pre-execution break
occurs, the PC of the instruction that set the break point is set in the SPC. SR when the
break occurs is set in SSR. H'1E0 is set in EXPEVT. The BL, MD, and RB bits in SR are
set to 1 and a branch occurs to PC = VBR + H'0100. See section 7, User Break Controller,
for more information.
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