SH7708 Datasheet, PDF (621/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table B.3 Register States in Reset and Power-Down States (cont)
Reset States
Power-Down States
Module Register
Power-On
Manual
Standby
Sleep
SCI
SCSMR
H'00
H'00
H'00
H'00^*10
SCBRR
SCSCR
H'FF
H'00
H'FF
H'00
H'FF
H'00
H'FF^*10
H'00^*10
SCTDR
H'FF
H'FF
H'FF
H'FF^*10
SCSSR
H'84
H'84
H'84
H'84^*10
SCRDR
H'00
H'00
H'00
H'00^*10
SCSPTR
Initialized^*9
Held
Held
Held
SCSCMR
Initialized^*11
Initialized^*11
Initialized^*11 Initialized^*11
Notes: 1. MD = 1, RB = 1, BL = 1, I3–I0 = B'1111
M, Q, S, T are undefined.
2. The SV bit is undefined, other bits = 0.
3. H'8000: NMI pin is high / H'0000: NMI pin is low.
4. Initialized in a power-on reset via the RESET pin.
Held in a power-on reset via the WDT.
5. Depends on the count clock mode.
6. Only the ENB bit is cleared.
7. CF bit is undefined, other bits = 0.
8. RTCEN and START are held, other bits = 0.
9. Bits 2 and 0 are undefined, other bits = 0
10. Held when SCI is operating, initialized when SCI is not used.
11. Bits 0, 2, and 3 are cleared, other bits are undefined.
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