SH7708 Datasheet, PDF (236/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit 1: OVIE
0
1
Description
Disables interrupt requests caused by OVF
value)
Enables interrupt requests caused by OVF
(Initial
Bit 0—Refresh Count Overflow Limit Select (LMTS): Indicates the count limit value to be
compared to the number of refreshes indicated in the refresh count register (RFCR). When the
value RFCR exceeds the value specified by LMTS, the OVF flag is set.
Bit 0: LMTS
0
1
Description
Count limit value is 1024
value)
Count limit value is 512
(Initial
1 0 . 2 . 1 0 Refresh Timer Counter (RTCNT)
RTCNT is a 16-bit read/write register containing an 8-bit counter that counts up on an input
clock. The clock select bits (CKS2–CKS0) in RTCSR select the input clock. When RTCNT
matches RTCOR, the OVF bit in RTCSR is set and RTCNT is cleared. RTCNT is initialized to
H'00 by a power-on reset; it continues incrementing after a manual reset; it is not initialized in
standby mode, but retains its contents.
Note:
The method for writing to RTCOR is different from that for general registers to prevent
inadvertent overwriting. Using a word transfer instruction, place B'10100101 in the upper
byte and the write data in the lower byte. For details, see section 10.2.13, Cautions on
Accessing Refresh Control Related Registers.
Bit: 15
14
13
12
11
10
9
8
Bit name: —
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
Bit name:
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
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