SH7708 Datasheet, PDF (127/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

When the priorities for multiple interrupt sources are set to the same level and such interrupts are
generated at the same time, they are handled according to the default order listed in table 6.4.
Updating of interrupt priority level setting registers A and B should only be performed when the
BL bit in the status register (SR) is set to 1. To prevent erroneous interrupt acknowledgment, first
read one or other of the interrupt priority level setting registers, then clear the BL bit to 0. This
will secure the necessary timing internally.
Table 6.4 Interrupt Exception Vectors and Rankings
Interrupt Source
INTEVT Interrupt
IPR (Bit Priority within Default
Code Priority (Initial Numbers) IPR Setting Priorit
Value)
Unit
y
NMI
H'1C0 16
—
—
High
IRL IRL3 –IRL0 = 0000 H'200 15
—
—
IRL3 –IRL0 = 0001 H'220 14
—
—
IRL3 –IRL0 = 0010 H'240 13
—
—
IRL3 –IRL0 = 0011 H'260 12
—
—
IRL3 –IRL0 = 0100 H'280 11
—
—
IRL3 –IRL0 = 0101 H'2A0 10
—
—
IRL3 –IRL0 = 0110 H'2C0 9
—
—
IRL3 –IRL0 = 0111 H'2E0 8
—
—
IRL3 –IRL0 = 1000 H'300 7
—
—
↓
IRL3 –IRL0 = 1001 H'320 6
—
—
IRL3 –IRL0 = 1010 H'340 5
—
—
IRL3 –IRL0 = 1011 H'360 4
—
—
IRL3 –IRL0 = 1100 H'380 3
—
—
IRL3 –IRL0 = 1101 H'3A0 2
—
—
IRL3 –IRL0 = 1110 H'3C0 1
—
—
TMU0 TUNI0*¹
H'400 0–15 (0)
IPRA (15–12) —
TMU1 TUNI1*¹
H'420 0–15 (0)
IPRA (11–8) —
TMU2 TUNI2*¹
H'440 0–15 (0)
IPRA (7–4) High
TMU2 TICPI2*²
H'460 0–15 (0)
IPRA (7–4) Low
Low
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