SH7708 Datasheet, PDF (258/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Basic Timing: Figure 10.14 shows the basic timing for DRAM access is 3 cycles. Tpc is the
precharge cycle, Tr the RAS assert cycle, Tc1 the CAS assert cycle, and Tc2 the read data latch
cycle.
CKIO
Tr
Tc1
Tc2
(Tpc)
A25 to A16
A15 to A0
RD/WR
RAS
CASxx
D31 to D0
(read)
D31 to D0
(write)
BS
CS2 or CS3
Figure 10.14 Basic Timing for DRAM Access
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