SH7708 Datasheet, PDF (227/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit 5—Memory Data Size (SZ): Specifies the memory data bus size for DRAM, synchronous
DRAM, and pseudo-SRAM. Always set this bit to 1 when synchronous DRAM is used. Takes
precedence over the BCR2 register designation.
Bit 5: SZ
0
1
Description
Word (16-bit)
value)
Longword (32-bit)
(Initial
Bits 4 and 3—Address Multiplex (AMX1, AMX0): These bits specify address multiplexing for
DRAM and synchronous DRAM. The actual address shift value differs between DRAM interface
and synchronous DRAM interface.
For DRAM Interface:
Bit 4: AMX1
0
1
Bit 3: AMX0
0
1
0
1
Description
8-bit column address product
value)
9-bit column address product
10-bit column address product
11-bit column address product
(Initial
For Synchronous DRAM Interface:
Bit 4: AMX1
0
1
Bit 3: AMX0
0
1
0
1
Description
16-Mbit product (1M × 16 bits)
value)
16-Mbit product (2M × 8 bits)
16-Mbit product (4M × 4 bits)
4-Mbit product (256k × 16 bits)
(Initial
Bit 2—Refresh Control (RFSH): Determines whether or not refreshing of DRAM, synchronous
DRAM, and pseudo-SRAM is performed. The timer for generation of the refresh request frequency
can also be used as an interval timer.
Bit 2: RFSH
0
1
Description
No refresh
value)
Refresh
(Initial
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