SH7708 Datasheet, PDF (568/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

A . 2 Pin Specifications
Table A.2 shows the pin specifications.
Table A.2 Pin Specifications
Pin
Pin No.
I/O
MD5/RAS2
130
I/O
MD4/CE2B
103
I/O
MD3/CE2A
104
I/O
MD2/RXD
84
I
MD1/TXD
85
I/O
MD0/SCK
86
I/O
STATUS1
97
O
STATUS0
98
O
A25 to A0
72 to 70,
O
67 to 61,
58 to 56,
53 to 51,
48 to 43,
40 to 37
D31 to D24
140 to 143,
I/O
1 to 4
D23 to D16/ 5, 8 to 14
I/O
Port 7 to Port 0
Function
Operating mode pin (endian switching)/RAS (for DRAM).
MD signal is fetched in at power-on reset.
Switched to RAS2 on area 2 DRAM enabling by register.
Operating mode pin (area 0 bus width)/PCMCIA CE pin.
MD signal is fetched in at power-on reset.
Switched to CE2B on area 6 PCMCIA enabling by
register.
Operating mode pin (area 0 bus width)/PCMCIA CE pin.
MD signal is fetched in at power-on reset.
Switched to CE2A on area 5 PCMCIA enabling by
register.
Operating mode pin/serial data input.
MD signal is fetched in at power-on reset.
Switched to RXD on SCI enabling by register.
Operating mode pin/serial data output.
MD signal is fetched in at power-on reset.
Switched to TXD on SCI enabling by register.
Operating mode pin/serial clock.
MD signal is fetched in at power-on reset.
Switched to SCK on SCI enabling by register.
Processor status
Processor status
Address bus
Data bus
Data bus / I/O port
554