SH7708 Datasheet, PDF (135/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 6.6 Interrupt Response Time (cont)
Number of States
Item
NMI
RL
Peripheral
Modules
Notes
Response Total
time
(5.5 + X) × Icyc (5.5 + X) × Icyc (5.5 + X) × Icyc
+ 0.5 × Bcyc + 0.5 × Bcyc + 1.5 × Pcyc
+ 0.5 × Pcyc + 2 × Pcyc
Minimum 6.5
8
7
At 60 MHz operation:
case*²
0.10–0.14 µs
Maximum 7 + S
case*³
13 + S
10.5 + S
At 60 MHz operation:
0.23–0.34 µs (in case of
operand cache-hit)
At 60 MHz operation:
0.27–0.37 µs (when
external memory
access is performed
with wait = 0)
Icyc: Duration of one cycle of internal clock supplied to CPU, etc.
Bcyc: Duration of one CKIO cycle
Pcyc: Duration of one cycle of peripheral clock supplied to supporting modules
Notes: 1. S also includes the memory access wait time.
The processing requiring the maximum execution time is LDC.L @Rm+, SR. When the
memory access is a cache-hit, this requires 7 instruction execution cycles. When
external access is performed, the corresponding number of cycles must be added.
There are also instructions that perform two external memory accesses; if external
memory access is slow, the number of instruction execution cycles will increase
accordingly.
2. The internal clock : CKIO : peripheral clock ratio is 1 : 1 : 1.
3. The internal clock : CKIO : peripheral clock ratio is 1 : 1 : 1/4.
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