SH7708 Datasheet, PDF (104/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

• The RB bit in SR is set to 1.
• An encoded value identifying the exception event is written to bits 11–0 of the EXPEVT
register.
• Instruction execution jumps to the vector location designated by either the sum of the vector
base address and offset H'00000400 in the vector table in a TLB miss trap, or by the sum of the
vector base address and offset H'00000100 for exceptions other than TLB miss traps, to invoke
the exception handler.
4 . 5 Individual Exception Operations
This section describes the conditions for specific exception handling, and the processor operations.
4.5.1 Resets
• Power-On Reset
 Conditions: BREQ pin high and RESET low
 Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC = H'A0000000.
Initialization sets the VBR register to H'0000000. In SR, the MD, RB and BL bits are set
to 1 and the IMASK field is set to B'1111. The CPU and on-chip supporting modules are
initialized. See the register descriptions in the relevant sections for details. A power-on reset
must always be performed when powering on.
• Manual Reset
 Conditions: BREQ pin low and RESET low
 Operations: EXPEVT set to H'020, VBR and SR initialized, branch to PC = H'A0000000.
Initialization sets the VBR register to H'0000000. In SR, the MD, RB, and BL bits are set
to 1 and the IMASK field is set to B'1111. The CPU and on-chip supporting modules are
initialized. See the register descriptions in the relevant sections for details.
Table 4.4 Types of Reset
Type
Power-on
reset
Manual
reset
Conditions for
Transition
to Reset State
BREQ
RESET
High
Low
Low
Low
CPU
Initialized
Initialized
Internal State
On-Chip Supporting
Modules
(See register configuration in
relevant sections)
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