SH7708 Datasheet, PDF (239/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

1 0 . 3 BSC Operation
1 0 . 3 . 1 Endian/Access Size and Data Alignment
The SH7708 Seires supports both big-endian mode, in which the 0 address is the most significant
byte in the byte data, and little-endian mode, in which the 0 address is the least significant byte.
Switching between the two is designated by an external pin (MD5 pin) at the time of a power-on
reset. After a power-on reset, big-endian mode is set when MD5 is low, and little-endian mode is
set when MD5 is high.
Three data bus widths are available for normal memory (byte, word, longword) and two data bus
widths (word and longword) for DRAM and pseudo-SRAM. Only longword is available for
synchronous DRAM. For the PCMCIA interface, choose from byte and word. This means data
alignment is done by matching the device’s data width and endian. The access unit must also be
matched to the device’s bus width. This also means that when longword data is read from a byte-
width device, four read operations must be executed. In the SH7708 Series, data alignment and
conversion of data length is performed automatically between the respective interfaces.
Tables 10.6 through 10.11 show the relationship between endian, device data width, and access
unit.
Table 10.632-Bit External Device/Big Endian Access and Data Alignment
Data Bus
Operation D31–D24D23–D16D15–D8D7–D0
Address 0 Data
—
byte access 7–0
—
—
Address 1 —
byte access
Data
—
—
7–0
Address 2 —
—
Data —
byte access
7–0
Address 3 —
—
—
Data
byte access
7–0
Address 0 Data
Data
—
—
word access 15–8
7–0
Address 2 —
—
Data Data
word access
15–8 7–0
Address 0
longword
access
Data
31–24
Data
23–16
Data
15–8
Data
7–0
Strobe Signal
WE3 , WE2 , WE1 , WE0 ,
CASHH , CASHL , CASLH , CASLL,
DQMUU DQMUL DQMLU DQMLL
Asserted —
—
—
—
Asserted —
—
—
—
Asserted —
—
—
—
Asserted
Asserted Asserted —
—
—
—
Asserted Asserted
Asserted Asserted Asserted Asserted
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