SH7708 Datasheet, PDF (195/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

9 . 1 0 Using the WDT
9.10.1 Canceling Standbys
The WDT can be used to cancel standby mode with an NMI or other interrupts. The procedure is
described below. (The WDT does not run when resets are used for canceling, so keep the RESET
pin low until the clock stabilizes.)
1. Before transitioning to standby mode, always clear the TME bit in WTCSR to 0. When the
TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count
overflows.
2. Set the type of count clock used in the CKS2–CKS0 bits in WTCSR and the initial values for
the counter in the WTCNT counter. These values should ensure that the time till count
overflow is longer than the clock oscillation settling time.
3. Move to standby mode by executing a SLEEP instruction to stop the clock.
4. The WDT starts counting by detecting the edge change of the NMI signal or detecting
interrupts.
5. When the WDT count overflows, the CPG starts supplying the clock and the processor
resumes operation. The WOVF flag in WTCSR is not set when this happens.
6. The counter stops at the values H'00–H'01. The stop value depends on the clock ratio.
9 . 1 0 . 2 Changing the Frequency
To change the frequency used by the PLL, use the WDT. When changing the frequency only by
switching the divider, do not use the WDT.
1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit
is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows.
2. Set the type of count clock used in the CKS2–CKS0 bits of WTCSR and the initial values for
the counter in the WTCNT counter. These values should ensure that the time till count
overflow is longer than the clock oscillation settling time.
3. When the frequency control register (FRQCR) is written, the clock stops and the processor
enters standby mode temporarily. The WDT starts counting.
4. When the WDT count overflows, the CPG resumes supplying the clock and the processor
resumes operation. The WOVF flag in WTCSR is not set when this happens.
5. The counter stops at the values H'00–H'01. The stop value depends on the clock ratio.
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