SH7708 Datasheet, PDF (277/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Burst Write: The timing chart for a burst write is shown in figure 10.26. In the SH7708 Series,
a burst write occurs only in the event of cache copy-back. In a burst write operation, following the
Tr cycle in which ACTV command output is performed, a WRIT command is issued in the Tc1,
Tc2, and Tc3 cycles, and a WRITA command that performs auto-precharge is issued in the Tc4
cycle. In the write cycle, the write data is output at the same time as the write command. For the
write with auto-precharge command, precharging of the relevant bank is performed in the
synchronous DRAM after completion of the write command, and therefore no command can be
issued for the same bank until precharging is completed. Consequently, in addition to the precharge
wait cycle, Tpc, used in a read access, cycle Trwl is added as a wait interval until precharging is
started, following the write command. Issuance of a new command for the same bank is postponed
during this interval. The number of Trwl cycles can be specified by the TRWL bit in MCR.
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