SH7708 Datasheet, PDF (315/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

1 1 . 2 . 2 Timer Start Register (TSTR)
TSTR is an 8-bit read/write register that selects whether to run or halt the timer counters (TCNT)
for channels 0–2. TSTR is initialized to H'00 by a power-on reset or manual reset. In standby
mode, when the PLL1 multiplication factor is changed in clock mode 0, 1, 2, or 7, or when the
MSTP2 bit is set to 1 in STBCR, TSTR is initialized only when the input clock selected for the
channel is an external clock (TCLK) or the peripheral clock (Pø).
Bit: 7
6
5
4
3
2
1
0
Bit name: —
—
—
—
—
STR2 STR1 STR0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R/W R/W R/W
Bits 7 to 3—Reserved: These bits always read 0. The write value should always be 0.
Bit 2—Counter Start 2 (STR2): Selects whether to run or halt timer counter 2 (TCNT2).
Bit 2: STR2
0
1
Description
Halt TCNT2 count
value)
Start TCNT2 counting
(Initial
Bit 1—Counter Start 1 (STR1): Selects whether to run or halt timer counter 1 (TCNT1).
Bit 1: STR1
0
1
Description
Halt TCNT1 count
value)
Start TCNT1 counting
(Initial
Bit 0—Counter Start 0 (STR0): Selects whether to run or halt timer counter 0 (TCNT0).
Bit 0: STR0
0
1
Description
Halt TCNT0 count
value)
Start TCNT0 counting
(Initial
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