SH7708 Datasheet, PDF (196/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

9 . 1 0 . 3 Using Watchdog Timer Mode
1. Set the WT/IT bit in the WTCSR register to 1, set the reset type in the RSTS bit, set the type
of count clock in the CKS2–CKS0 bits, and set the initial value of the counter in the WTCNT
counter.
2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode.
3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent
the counter from overflowing.
4. When the counter overflows, the WDT sets the WOVF flag in WTCSR to 1 and generates the
type of reset specified by the RSTS bit. The counter then resumes counting.
9 . 1 0 . 4 Using Interval Timer Mode
When operating in interval timer mode, interval timer interrupts are generated at every overflow of
the counter. This enables interrupts to be generated at set periods.
1. Clear the WT/IT bit in the WTCSR register to 0, set the type of count clock in the CKS2–
CKS0 bits, and set the initial value of the counter in the WTCNT counter.
2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode.
3. When the counter overflows, the WDT sets the IOVF flag in WTCSR to 1 and an interval
timer interrupt request is sent to INTC. The counter then resumes counting.
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