SH7708 Datasheet, PDF (224/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

• For Normal Memory
Bit 4: A1-2W0
0
1
Bit 3: A1-2W0
0
1
0
1
Description
Inserted Wait States WAIT Pin
0
Ignored
1
Enabled
2
Enabled
3
Enabled (Initial value)
• For DRAM, Synchronous DRAM
Description
Bit 4: A1-2W0 Bit 3: A1-2W0 DRAM: CAS Assert Period SDRAM: CAS Latency
0
0
1
1
1
1
1
1
0
2
2
1
3
3
(Initial value)
Bits 2 to 0—Area 0 Wait Control (A0W2, A0W1, A0W0): These bits specify the number of wait
states inserted in physical space area 0. They also specify the burst pitch for burst transfer.
Bit 2:
A0W2
0
1
Bit 1:
A0W1
0
1
0
1
Bit 0:
A0W0
0
1
0
1
0
1
0
1
Description
First Cycle
Burst Cycle
(Excluding First Cycle)
Inserted
Number of States
Wait States WAIT Pin Per Data Transfer WAIT Pin
0
Ignored
2
Enabled
1
Enabled 2
Enabled
2
Enabled 3
Enabled
3
Enabled 4
Enabled
4
Enabled 4
Enabled
6
Enabled 6
Enabled
8
Enabled 8
Enabled
10 (Initial value) Enabled 10
Enabled
1 0 . 2 . 5 Individual Memory Control Register (MCR)
The individual memory control register (MCR) is a 16-bit read/write register that specifiesRAS
and CAS timing and burst control for DRAM (area 3 only), synchronous DRAM (areas 2 and 3),
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