SH7708 Datasheet, PDF (235/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit 6: CMIE
0
1
Description
Disables the interrupt request caused by CMF
value)
Enables the interrupt request caused by CMF
(Initial
Bits 5 to 3—Clock Select Bits (CKS2–CKS0): These bits select the clock input to RTCNT. The
source clock is the external bus clock (CKIO). The RTCNT count clock is CKIO scaled by the
specified ratio.
Bit 5: CKS2 Bit 4: CKS1 Bit 3: CKS0 Description
0
0
0
Disables clock input
value)
1
Bus clock (CKIO)/4
1
0
CKIO/16
1
CKIO/64
1
0
0
CKIO/256
1
CKIO/1024
1
0
CKIO/2048
1
CKIO/4096
(Initial
Bit 2—Refresh Count Overflow Flag (OVF): Status flag that indicates when the number of refresh
requests indicated in the refresh count register (RFCR) exceeds the limit set in the LMTS bit in
RTCSR.
Bit 2: OVF
Description
0
RFCR has not exceeded the count limit value set in LMTS
Clearing Condition: When 0 is written to OVF
(Initial
value)
1
RFCR has exceeded the count limit value set in LMTS
Setting Condition: When the RFCR value has exceeded the count limit value
set in LMTS*
Note: Contents do not change when 1 is written to OVF.
Bit 1—Refresh Count Overflow Interrupt Enable (OVIE): Selects whether to suppress generation
of interrupt requests by OVF when the OVF bit of RTCSR is set to 1.
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