SH7708 Datasheet, PDF (130/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

6 . 3 . 2 Interrupt Control Register (ICR)
ICR is a 16-bit register that sets the input signal detection mode of the external interrupt input pin
NMI and indicates the input signal level to the NMI pin. This register is initialized by a power-on
reset or manual reset. It is not initialized in standby mode.
Bit: 15
14
13
12
11
10
9
8
Bit name: NMIL
—
—
—
—
—
—
NMIE
Initial value: 0/1*
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R/W
Bit: 7
6
5
4
3
2
1
0
Bit name: —
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Note: When NMI input is high: 1; when NMI input is low: 0.
Bit 15—NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can
be read to determine the NMI pin level. It cannot be modified.
Bit 15: NMIL
0
1
Description
NMI input level is low
NMI input level is high
Bit 8—NMI Edge Select (NMIE): Selects whether the falling or rising edge of the interrupt request
signal to the NMI is detected.
Bit 8: NMIE
0
1
Description
Interrupt request is detected on the falling edge of NMI input
(Initial value)
Interrupt request is detected on rising edge of NMI input
Bits 14–9 and 7–0—Reserved: These bits always read 0. The write value should always be 0.
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