SH7708 Datasheet, PDF (234/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

1 0 . 2 . 9 Refresh Timer Control/Status Register (RTCSR)
The refresh timer control/status register (RTSCR) is a 16-bit read/write register that specifies the
refresh cycle, whether to generate an interrupt, and the cycle of that interrupt. RTSCR is initialized
to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode.
Note:
The method for writing to RTCOR is different from that for general registers to prevent
inadvertent overwriting. Using a word transfer instruction, place B'10100101 in the upper
byte and the write data in the lower byte. For details, see section 10.2.13, Cautions on
Accessing Refresh Control Related Registers.
Bit: 15
14
13
12
11
10
9
8
Bit name: —
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit:
Bit name:
Initial value:
R/W:
7
CMF
0
R/W
6
CMIE
0
R/W
5
CKS2
0
R/W
4
CKS1
0
R/W
3
CKS0
0
R/W
2
OVF
0
R/W
1
OVIE
0
R/W
0
LMTS
0
R/W
Bits 15 to 8—Reserved: These bits always read 0.
Bit 7—Compare Match Flag (CMF): Status flag that indicates that the values of RTCNT and
RTCOR match.
Bit 7: CMF
Description
0
The values of RTCNT and RTCOR do not match.
Clearing condition: When a refresh is performed after 0 has been written in
CMF and RFSH = 1 and RMODE = 0 (to perform a CBR refresh).
(Initial
value)
1
The values of RTCNT and RTCOR match.
Setting condition: RTCNT = RTCOR*
Note: Contents do not change when 1 is written to CMF.
Bit 6—Compare Match Interrupt Enable (CMIE): Enables or disables an interrupt request caused
when the CMF bit in RTCSR is set to 1. Do not set this bit to 1 when using CAS-before-RAS
refreshing or auto-refreshing.
220