SH7708 Datasheet, PDF (220/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Wait state control register 1 (WCR1) is a 16-bit read/write register that specifies the number of idle
(wait) state cycles inserted for each area. For some memories, the drive of the data bus may not be
turned off quickly even when the read signal from the external device is turned off. This can result
in conflicts between data buses when consecutive memory accesses are to different memories or
when a write immediately follows a memory read. The SH7708 Series automatically inserts idle
states equal to the number set in WCR1 in those cases.
WCR1 is initialized to H'3FFF by a power-on reset. It is not initialized by a manual reset or in
standby mode, but retains its contents.
Bit: 15
Bit name: —
Initial value: 0
R/W: R
14
13
12
11
10
9
8
— A6IW1 A6IW0 A5IW1 A5IW0 A4IW1 A4IW0
0
1
1
1
1
1
1
R
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 7
6
5
4
3
2
1
Bit name: A3IW1 A3IW0 A2IW1 A2IW0 A1IW1 A1IW0 A0IW1
Initial value: 1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W
Bits 15, 14 —Reserved: These bits always read 0. The write value should always be 0.
0
A0IW0
1
R/W
Bits 2n + 1, 2n—Area n (6–0) Intercycle Idle Specification (AnIW1, AnIW0): These bits specify
the number of idles inserted between bus cycles when switching between physical space area n (6–
0) to another space or between a read access to a write access in the same physical space.
Bit 2n + 1:
AnIW1
0
1
Bit 2n: AnIW0 Description
0
No idle cycles
1
1 idle cycle inserted
0
2 idle cycles inserted
1
3 idle cycles inserted
value)
(Initial
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