SH7708 Datasheet, PDF (403/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 13.14 SCSSR Status Flags and Transfer of Receive Data
Receive Error Status
SCSSR Status Flags _{Receive Data}
Transfer
RDRF ORER FER P E R SCRSR → SCRDR
Overrun error
1
1
00
X
Framing error
0
0
10
O
Parity error
0
0
01
O
Overrun error + framing error
1
1
10
X
Overrun error + parity error
1
1
01
X
Framing error + parity error
0
0
11
O
Overrun error + framing error + parity error 1
1
11
X
O: Receive data is transferred from SCRSR to SCRDR.
X: Receive data is not transferred from SCRSR to SCRDR.
Break Detection and Processing: Break signals can be detected by reading the RxD pin
directly when a framing error (FER) is detected. In the break state, the input from the RxD pin
consists of all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state,
the SCI receiver continues to operate, so if the FER bit is cleared to 0, it will be set to 1 again.
Sending a Break Signal: The input/output direction and level of the TxD pin can be set using
the SPB0IO and SPB0DT bits in the serial port register (SCSPTR). Use these bits to send breaks.
After initialization, the pin will not function as a TxD pin until the TE bit is set to 1 (enabling
transmission). Through this period, the value of the SPB0DT bit substitutes for the mark state.
For this reason, the SPB0IO and SPB0DT bits are initially set to 1 (output, high level). To send a
break during serial transmission, clear the SPB0DT bit to 0 (low level), then clear TE to 0 (halting
transmission). When the TE bit is cleared to 0, the transmitter is initialized without regard to the
current transmission status, and 0 is output from the TxD pin.
Receive Error Flags and Transmitter Operation (Synchronous Mode Only): When
a receive error flag (ORER, PER, or FER) is set to 1, the SCI will not start transmitting even if
TDRE is set to 1. Be sure to clear the receive error flags to 0 before starting to transmit. Note that
clearing RE to 0 does not clear the receive error flags.
Receive Data Sampling Timing and Receive Margin in Asynchronous Mode: I n
asynchronous mode, the SCI operates on a base clock of 16 times the transfer rate frequency. In
receiving, the SCI synchronizes internally with the falling edge of the start bit, which it samples
on the base clock. Receive data is latched on the rising edge of the eighth base clock pulse (figure
13.21).
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