SH7708 Datasheet, PDF (67/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

3 . 1 . 3 SH7708 Series MMU
Virtual Address Map: The SH7708 Series uses 32-bit virtual addresses to access a 4-Gbyte
virtual address space that is divided into several areas. Address space mapping is shown in figure
3.2.
In privileged mode, there are five areas, P0–P4. The P0 and P3 areas are mapped onto physical
address space in page units, in accordance with address translation table information. Addresses
H'7F000000–H'7FFFFFFF in the P0 area can be used as on-chip RAM space by making a setting
in the cache control register (CCR) (see section 5, Cache). In this case, mapping by means of the
address translation table is not performed for the on-chip RAM space. Write-back or write-through
can be selected for write access by means of a CCR setting.
Mapping of the P1 area is fixed to physical address space (H'00000000 to H'1FFFFFFF). In the
P1 area, setting a virtual address MSBs (bit 31) to 0 generates the corresponding physical address.
P1 area access can be cached, and the cache control register (CCR) is set to indicate whether to
cache or not. Write access is processed as write-through (SH7708). A CCR setting can be made to
select write-back or write-through.
Mapping of the P2 area is fixed to physical address space (H'00000000 to H'1FFFFFFF). In the
P2 area, setting the top three virtual address bits (bits 31, 30, and 29) to 0 generates the
corresponding physical address. P2 area access cannot be cached.
The P1 and P2 areas are not mapped by the address translation table, so the TLB is not used and no
exceptions like TLB misses occur. Initialization of MMU-related registers, exception processing
handling, and the like are located in the P1 and P2 areas. Because the P1 area is cached, handlers
that require high-speed processing are placed there.
The P4 area is used for mapping on-chip control register addresses.
In user mode, the 2 Gbytes of virtual address space from H'00000000 to H'7FFFFFFF (area U0)
can be accessed. U0 is mapped onto physical address space in page units. As with the P0 area,
addresses H'7000000–H'7FFFFFFF can be used as on-chip RAM space by making a setting in the
cache control register (CCR). In this case, mapping by means of the address translation table is not
performed for the on-chip RAM space. The 2 Gbytes of virtual address space from H'80000000 to
H'FFFFFFFF cannot be accessed in user mode. Attempting to do so creates an address error.
Write-back or write-through mode can be selected for write accesses by means of a CCR setting.
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