SH7708 Datasheet, PDF (154/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

5. If data access (address + data) is set as a break condition, and the instruction following that at
which that break condition was matched is a SLEEP instruction, the condition match flag will
be set but a break will not be executed. The SLEEP instruction will be processed correctly.
6. If an instruction fetch (halt after execution) is set as a break condition, and a nonmaskable
interrupt is detected at the instruction following that at which that break condition was
matched, the condition match flag will be set but a break will not be executed. The
nonmaskable interrupt will be processed correctly.
7. When a sequential break setting is made, a condition match occurs on a channel B match in a
bus cycle after that in which a channel A match occurred. Therefore, a condition match will not
be recognized if bus cycles occurring simultaneously in channel A and B are designated. Also,
since the CPU has a pipeline structure, the order of instruction fetch and data access cycles is
determined by the pipeline. With sequential conditions, therefore, the sequential conditions will
be taken as being matched as long as the respective channel conditions match in the order in
which the bus cycles occur.
8. With an emulator, the UBC is used on the emulator system side in order to implement the
emulator’s break functions. Consequently, no UBC functions can be used when an emulator is
used.
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