SH7708 Datasheet, PDF (132/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Program
execution state
Interrupt
No
generated?
Yes
(SR. BL
= 0) or (sleep ^No
or standby
mode)?
Yes
No
NMI?
Yes
Level 15 ^No
interrupt?
Yes
Level 14
No
Yes
I3–I0 level
interrupt?
14 or lower?
Yes
Level 1
No
IRQOUT = low
No _Yes
I3–I0 level
13 or lower?
interrupt?
Yes
Set interrupt
cause in INTEVT
No _Yes
I3–I0
level 0?
No
Save SR to SSR;
save PC to SPC
Set BL/MD/RB
bits in SR to 1
Branch to exception
handler
I3–I0: Interrupt mask bits in status register (SR)
Figure 6.3 Interrupt Operation Flowchart
118