SH7708 Datasheet, PDF (218/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bits 4 to 2—Area 2, Area 3 Memory Type (DRAMTP2, DRAMTP1, DRAMTP0): These bits
designate the types of memory connected to physical space areas 2 and 3. Normal memory, such as
ROM, SRAM, or flash RAM, can be directly connected. Pseudo-SRAM, DRAM, and
synchronous DRAM can also be directly connected.
Bit 4:
DRAMTP2
Bit 3:
DRAMTP1
Bit 2:
DRAMTP0
Description
0
0
0
Areas 2 and 3 are normal memory
(Initial
value)
1
Area 2: normal memory; area 3: PSRAM
1
0
Area 2: normal memory; area 3: SDRAM
1
Areas 2 and 3 are SDRAM
1
0
0
Area 2: normal memory; area 3: DRAM
1
Areas 2 and 3 are DRAM *
1
0
Reserved (cannot be set)
1
Reserved (cannot be set)
Note: When selecting these bits, set the area 2 and 3 bus widths as word. The MD5 pin output is
the RAS2 signal.
Bit 1—Area 5 Bus Type (A5PCM): Designates whether to access physical space area 5 as
PCMCIA space.
Bit 1: A5PCM
Description
0
Access physical space area 5 as normal memory.
1
Access physical space area 5 as PCMCIA space.*
Note: MD3 pin output is CE2A.
(Initial value)
Bit 0—Area 6 Bus Type (A6PCM): Designates whether to access physical space area 6 as
PCMCIA space.
Bit 0: A6PCM
Description
0
Access physical space area 6 as normal memory.
1
Access physical space area 6 as PCMCIA space.*
Note: MD4 pin output is CE2B.
(Initial value)
1 0 . 2 . 2 Bus Control Register 2 (BCR2)
Bus control register 2 (BCR2) is a 16-bit read/write register that selects the bus size of each area,
and whether to use the 8-bit port. It is initialized to H'3FFC by a power-on reset, but is not
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