SH7708 Datasheet, PDF (10/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

10.1.5 Area Overview.......................................................................................193
10.1.6 PCMCIA Support ..................................................................................196
10.2 BSC Registers...................................................................................................200
10.2.1 Bus Control Register 1 (BCR1) ................................................................200
10.2.2 Bus Control Register 2 (BCR2) ................................................................203
10.2.3 Wait State Control Register 1 (WCR1) ......................................................204
10.2.4 Wait State Control Register 2 (WCR2) ......................................................205
10.2.5 Individual Memory Control Register (MCR) ...............................................208
10.2.6 DRAM Control Register (DCR) ...............................................................213
10.2.7 PCMCIA Control Register (PCR).............................................................215
10.2.8 Synchronous DRAM Mode Register (SDMR) .............................................216
10.2.9 Refresh Timer Control/Status Register (RTCSR) .........................................217
10.2.10 Refresh Timer Counter (RTCNT) ............................................................219
10.2.11 Refresh Time Constant Register (RTCOR)................................................220
10.2.12 Refresh Count Register (RFCR)..............................................................220
10.2.13 Cautions on Accessing Refresh Control Related Registers ............................221
10.3 BSC Operation..................................................................................................222
10.3.1 Endian/Access Size and Data Alignment .....................................................222
10.3.2 Description of Areas ...............................................................................228
10.3.3 Basic Interface........................................................................................231
10.3.4 DRAM Interface.....................................................................................237
10.3.5 Synchronous DRAM Interface ..................................................................253
10.3.6 Pseudo-SRAM Direct Connection .............................................................269
10.3.7 Burst ROM Interface...............................................................................278
10.3.8 PCMCIA Interface..................................................................................281
10.3.9 Waits between Access Cycles ...................................................................293
10.3.10 Bus Arbitration ....................................................................................294
Section 11 Timer (TMU)...............................................................297
11.1 Overview..........................................................................................................297
11.1.1 Features................................................................................................297
11.1.2 Block Diagram.......................................................................................297
11.1.3 Pin Configuration ..................................................................................299
11.1.4 Register Configuration ............................................................................299
11.2 TMU Registers..................................................................................................300
11.2.1 Timer Output Control Register (TOCR) .....................................................300
11.2.2 Timer Start Register (TSTR) ....................................................................301
11.2.3 Timer Control Register (TCR)..................................................................302
11.2.4 Timer Constant Register (TCOR)..............................................................305
11.2.5 Timer Counters (TCNT) ..........................................................................306
11.2.6 Input Capture Register (TCPR2)...............................................................307
11.3 TMU Operation.................................................................................................308
11.3.1 Overview ..............................................................................................308
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