SH7708 Datasheet, PDF (34/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Address A + 1 Address A + 3 Address A + 10 Address A + 8
Address A Address A + 2 Address A + 11 Address A + 9
31 23 15 7 0 31 23 15 7 0
Address A Byte0 Byte1 Byte2 Byte3 Byte3 Byte2 Byte1 Byte0
Address A + 4
Word0
Word1
Word1
Word0
Address A + 8
Longword
Longword
Address A + 8
Address A + 4
Address A
Big-endian mode
Little-endian mode
Figure 2.7 Byte, Word, and Longword Alignment
2 . 3 Instruction Features
2 . 3 . 1 Execution Environment
Data Length: The SH7708 Series instruction set is implemented with fixed-length 16-bit wide
instructions executed in a pipelined sequence with single-cycle execution for most instructions. All
operations are executed in 32-bit longword units. Memory can be accessed in 8-bit byte, 16-bit
word, or 32-bit longword units, with byte or word units sign-extended into 32-bit longwords.
Literals are sign-extended in arithmetic operations (MOV, ADD, and CMP/EQ instructions) and
zero-extended in logical operations (TST, AND, OR, and XOR instructions).
Load/Store Architecture: The SH7708 Series features a load-store architecture in which basic
operations are executed in registers. Operations requiring memory access are executed in registers
following register loading, except for bit-manipulation operations such as logical AND functions,
which are executed directly in memory.
Delayed Branching: Unconditional branching is implemented as delayed branch operations.
Pipeline disruptions due to branching are minimized by the execution of the instruction following
the delayed branch instruction prior to branching. Conditional branch instructions are of two kinds,
delayed and normal.
BRA
TRGET
ADD
R1, R0 ;ADD is executed prior to branching to TRGET
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