SH7708 Datasheet, PDF (216/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit 12: HIZCNT
0
1
Description
RAS and CAS signals become high-impedance (High-Z) in standby mode and
in bus-released state.
(Initial
value)
RAS and CAS signals drive in standby mode and in bus-released state.
Bit 11—Endian Flag (ENDIAN): Samples the value of the external pin designating endian upon a
power-on reset. Endian for all physical spaces is decided by this bit, which is read-only.
Bit 11: ENDIAN
0
1
Description
(On reset) Endian setting external pin (MD5) is low. Indicates the SH7708
Series is set as big-endian.
(On reset) Endian setting external pin (MD5) is high. Indicates the SH7708
Series is set as little-endian.
Bits 10 and 9—Area 0 Burst ROM Control (A0BST1–A0BST0): These bits specify whether to use
burst ROM in physical space area 0. When burst ROM is used, they set the number of burst
transfers.
Bit 10: A0BST1 Bit 9: A0BST0
0
0
1
1
0
1
Description
Access area 0 as normal memory.
(Initial value)
Access area 0 as burst ROM (4 consecutive accesses).
Can be used when bus width is 8, 16, or 32.
Access area 0 as burst ROM (8 consecutive accesses).
Can be used only when bus width is 8 or 16.
Access area 0 as burst ROM (16 consecutive
accesses). Can be used only when bus width is 8.
Bits 8 and 7—Area 5 Burst Enable (A5BST1–A5BST0): These bits specify whether to use burst
ROM and PCMCIA burst mode in physical space area 5. When burst ROM and PCMCIA burst
mode are used, they set the number of burst transfers.
202