SH7708 Datasheet, PDF (41/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 2.3 Instruction Formats (cont)
Instruction Format
Source
Operand
nm format 15
0 mmmm: register
xxxx nnnn mmmm xxxx direct
Destination
Operand
nnnn: register
direct
Instruction
Example
ADD Rm,Rn
md format 15
xxxx
nd4 format 15
xxxx
mmmm: register nnnn: register MOV.L
direct
indirect
Rm,@Rn
mmmm: register
indirect with post-
increment
(multiply-and-
accumulate
operation)
MACH,MACL
MAC.W
@Rm+,@Rn+
nnnn: * register
indirect with post-
increment
(multiply-and-
accumulate
operation)
mmmm: register nnnn: register
indirect with post- direct
increment
MOV.L
@Rm+,Rn
mmmm: register
direct
nnnn: register
indirect with
pre-decrement
MOV.L
Rm,@–Rn
mmmm: register nnnn: indexed MOV.L
direct
register indirect Rm,@(R0,Rn)
0 mmmmdddd:
R0 (register
xxxx mmmm dddd register indirect direct)
with displacement
MOV.B
@(disp,Rm),R0
0 R0 (register
xxxx nnnn dddd ^direct)
nnnndddd:
register indirect
with
displacement
MOV.B
R0,@(disp,Rn)
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