SH7708 Datasheet, PDF (66/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

this case, the MMU will generate an exception, change the physical memory mapping, and record
the new address translation information.
Although the functions of the MMU could also be implemented by software alone, the need for
translation to be performed by software each time a process accesses physical memory would result
in poor efficiency. For this reason, a buffer for address translation (translation lookaside buffer:
TLB) is provided in hardware to hold frequently used address translation information. The TLB can
be described as a cache for storing address translation information. Unlike cache memory, however,
if address translation fails—that is, if an exception is generated—switching of address translation
information is normally performed by software. This makes it possible for memory management
to be performed flexibly by software.
The MMU has two methods of mapping from virtual memory to physical memory: a paging
method using fixed-length address translation, and a segment method using variable-length address
translation. With the paging method, the unit of translation is a fixed-size address space (usually of
1 to 64 kbytes) called a page.
In the following text, SH7708 Series address space in virtual memory is referred to as virtual
address space, and address space in physical memory as physical memory space.
Process 1
Physical
memory
Process 1
Physical
memory
Process 1
Virtual
memory
MMU
Physical
memory
(1)
Process 1
Physical
memory
Process 2
(2)
Process 1
Process 2
Virtual
memory
MMU
Physical
memory
Process 3
Process 3
(3)
(4)
Figure 3.1 MMU Functions
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