SH7708 Datasheet, PDF (309/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

1 0 . 3 . 9 Waits between Access Cycles
A problem associated with higher external memory bus operating frequencies is that data buffer
turn-off on completion of a read from a low-speed device may be too slow, causing a collision
with data in the next access. This results in lower reliability or incorrect operation. To avoid this
problem, a data collision prevention feature has been provided. This memorizes the preceding
access area and the kind of read/write. If there is a possibility of a bus collision when the next
access is started, a wait cycle is inserted before the access cycle thus preventing a data collision.
There are two cases in which a wait cycle is inserted: when an access is followed by an access to a
different area, and when a read access is followed by a write access from the SH7708 Series. When
the SH7708 Series performs consecutive write cycles, the data transfer direction is fixed (from the
SH7708 Series to other memory) and there is no problem. With read accesses to the same area, in
principle, data is output from the same data buffer, and wait cycle insertion is not performed. Bits
AnIW1 and AnIW0 (n = 0–6) in WCR1 specify the number of idle cycles to be inserted between
access cycles when a physical space area access is followed by an access to another area, or when
the SH7708 Series performs a write access after a read access to physical space area n. If there is
originally space between accesses, the number of idle cycles inserted is the specified number of idle
cycles minus the number of empty cycles.
Waits are not inserted between accesses when bus arbitration is performed, since empty cycles are
inserted for arbitration purposes.
CKIO
T1
T2 Twait T1
T2 Twait T1
T2
A25 to A0
CSm
CSn
BS
RD/WR
RD
D31 to D0
Area m read
Area n space read
Area n space write
Area m inter-access wait specification Area n inter-access wait specification
Figure 10.49 Waits between Access Cycles
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