SH7708 Datasheet, PDF (121/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Section 6 Interrupt Controller (INTC)
6 . 1 Overview
The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt
requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the
user to handle interrupt requests according to the user-set priority.
6.1.1 Features
INTC has the following features:
• 15 levels of interrupt priority can be set: By setting the two interrupt-priority registers, the
priorities of on chip supporting module interrupts can be selected from 15 levels for different
request sources.
• NMI noise canceller function: NMI input level bit indicates NMI pin status. By reading this bit
in the interrupt exception handler, the pin status can be checked, enabling it to be used as a
noise canceler.
• External devices can be notified that an interrupt has been received (IRQOUT pin): For
example, when the SH7708 Series has released the bus, the external bus master can be notified
of the fact that an external interrupt, an on-chip supporting module interrupt, or a memory
refresh request has occurred, enabling the SH7708 Series to request the bus.
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