SH7708 Datasheet, PDF (267/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Figure 10.20 shows the timing of the CAS-before-RAS refresh cycle.
The number of RAS assert cycles in the refresh cycle is specified by the TRAS bits in MCR and
DCR. The specification of the RAS precharge time in the refresh cycle is determined by the setting
of the TPC bits in MCR and DCR in the same way as for normal access.
TRc
TRr1
TRr2
(Tpc)
CKIO
RAS
CASxx
RD/WR
CS2 or CS3
(High)
Figure 10.20 DRAM CAS-Before-RAS Refresh Cycle Timing
The self-refreshing supported by the SH7708 Series is shown in figure 10.21.
After the self-refresh is cleared, the refresh controller immediately generates a refresh request. The
RAS precharge time immediately after the end of the self-refreshing can be set by the TPC bits in
MCR and DCR.
DRAMs include low-power products (L versions) with a long refresh cycle time (for example, the
L version of the HM51W4160AL has a refresh cycle of 1024 cycles/128 ms compared with 1024
cycles/16 ms for the normal version). With these DRAMs, however, the same refresh cycle as the
normal version is requested only when refreshing immediately after self-refreshing. Therefore, to
ensure efficient DRAM refreshing, an overflow interrupt is generated and the refresh cycle is
restored to its proper value. This occurs after the necessary CAS-before-RAS refreshing has been
performed following self-refreshing of an L-version DRAM, using RFCR and the OVF, OVIE,
and LMTS bits in RTCSR. The procedure is as follows.
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