SH7708 Datasheet, PDF (223/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bits 6 and 5—Area 3 Wait Control (A3W1, A3W0): These bits specify the number of wait states
inserted in physical space area 3. External wait input is enabled only when normal memory is
used, and is ignored when DRAM, synchronous DRAM, or pseudo-SRAM is used.
• For Normal Memory
Bit 6: A3W0
0
1
Bit 5: A3W0
0
1
0
1
Description
Inserted Wait States WAIT Pin
0
Ignored
1
Enabled
2
Enabled
3
Enabled (Initial value)
• For DRAM, SDRAM, Pseudo-SRAM
Bit 6: A3W1 Bit 5: A3N0
0
0
1
1
0
1
DRAM: CAS
Assert Period
1
1
2
3
Description
SDRAM: CAS
Latency
1
1
2
3
PSRAM: OE, W E
Assert Period
1
1
2
3 (Initial value)
Bits 4 and 3—Areas 1 and 2 Wait Control (A1–2W1, A1–2W0): These bits specify the number of
wait states inserted in physical space areas 1 and 2. External wait input is enabled only when
normal memory is used, and is ignored when DRAM or synchronous DRAM is used.
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