SH7708 Datasheet, PDF (42/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 2.3 Instruction Formats (cont)
Instruction Format
Source
Operand
Destination Instruction
Operand
Example
nmd format15
0 mmmm: register
xxxx nnnn mmmm dddd ^direct
nnnndddd:
register
indirect with
displacement
MOV.L
Rm,@(disp,Rn)
mmmmdddd:
nnnn: register MOV.L
register indirect direct
@(disp,Rm),Rn
with displacement
d format
15
xxxx
xxxx
0 dddddddd: GBR
dddd dddd ^{indirect with}
displacement
R0 (register
direct)
MOV.L
@(disp,GBR),R0
R0 (register
direct)
dddddddd:
GBR indirect
with
displacement
MOV.L
R0,@(disp,GBR)
dddddddd:
PC-relative with
displacement
R0 (register
direct)
MOVA
@(disp,PC),R0
dddddddd:
—
PC-relative
BF label
d12 format 15
0 dddddddddddd: —
xxxx dddd dddd dddd PC-relative
BRA label
(label = disp +
PC)
nd8 format 15
0 dddddddd:
xxxx nnnn dddd dddd ^{PC-relative with}
displacement
nnnn: register MOV.L
direct
@(disp,PC),Rn
i format 15
0 iiiiiiii: immediate
xxxx xxxx i i i i i i i i
Indexed GBR
indirect
AND.B
#imm,
@(R0,GBR)
iiiiiiii: immediate
R0 (register
direct)
AND
#imm,R0
iiiiiiii: immediate —
TRAPA #imm
ni format 15
0 iiiiiiii: immediate
xxxx nnnn i i i i i i i i
nnnn: register ADD
direct
#imm,Rn
Note: In a multiply-and-accumulate instruction, nnnn is the source register.
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