SH7708 Datasheet, PDF (63/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

From any state except
hardware standby mode when
RESET = 0 and BREQ = 1
From any state except
hardware standby mode when
RESET = 0 and BREQ = 0
Power-on reset
state
RESET = 1,
BREQ = 1
RESET = 0,
BREQ = 1
Manual reset
state
Reset state
RESET = 1,
BREQ = 0
Exception-handling state
Interrupt
Bus-released
stateBBususrereqquuceeBlessuttascrlaernearcqaEieunnecxteesctrerputpiot ⁿ
End of exception
transition
processing
Bus _request
Program execution state
Bus
request
Bus
request
clearance
SLEEP
instruction
with STBY
bit cleared
SLEEP
instruction
with STBY
bit set
Interrupt
Sleep mode
CA = 1, RESET = 0, BREQ = 1
Hardware standby mode*
Standby mode
Power-down state
Note: Driving the CA pin low in any state will cause a transition to hardware standby mode (SH7708S,SH7708R only).
Figure 2.8 Processor State Transitions
2 . 5 . 2 Processor Modes
There are two processor modes: privileged mode and user mode. The processor mode is determined
by the processor mode bit (MD) in the status register (SR). User mode is selected when the MD
bit is 0, and privileged mode when the MD bit is 1. When the reset state or exception state is
entered, the MD bit is set to 1. When exception handling ends, the MD bit is cleared to 0 and user
mode is entered. There are certain registers and bits which can only be accessed in privileged mode.
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