SH7708 Datasheet, PDF (257/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Address Multiplexing: When areas 2 and 3 are designated as DRAM space, address
multiplexing is always performed in accesses to DRAM. This enables DRAM, which requires row
and column address multiplexing, to be connected directly to the SH7708 Series without using an
external address multiplexer circuit. Any of the four multiplexing methods shown below can be
selected by setting bits AMX1 and AMX0 in MCR for area 3 DRAM, or bits AMX1 and AMX0
in DCR for area 2 DRAM. The relationship between bits AMX1 and AMX0 and address
multiplexing is shown in table 10.12. The address output pins subject to address multiplexing are
A15 to A1. Pins A25 to A16 carry the original address.
Table 10.12 Relationship between AMX1-0 and Address Multiplexing
Setting
AMX1 AMX0
0
0
0
1
1
0
1
1
Number of Column
Address Bits
Output Timing
8 bits
Column address
Row address
9 bits
Column address
Row address
10 bits
Column address
Row address
11 bits
Column address
Row address
External Address Pins
A1 to A14
A15
A9 to A22
A23
A1 to A14
A15
A10 to A23 A24
A1 to A14
A15
A11 to A24 A25
A1 to A14
A15
A12 to A25 A15
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