SH7708 Datasheet, PDF (499/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

16.3.10 Peripheral Module Signal Timing
Table 16.11 Peripheral Module Signal Timing (Conditions: V_CC = 3.3 ± 0.3 V, Ta = 0 to
75°C)
–15
–30
–60
Module Item
Symbol Min Max Min Max Min Max Unit Figure
TMU,
RTC
Timer input setup time t_CLKS1
Timer clock input setup t_CKS
time
20 — 15 — 12 — ns 16.54,
20 — 15 — 12 — ns ^16.55
Timer clock;Single edge t_TCKWH
pulse width;Both _{edges tTCKWL}
1.5 —
2.5 —
1.5 —
2.5 —
1.5 —
2.5 —
tcyc
tcyc
Oscillation settling time t_ROSC — 3 — 3 — 3 S 16.61
SCI
Input clock cycle;
t_SCYC
4 — 4 — 4 — tcyc 16.62–
Asynchronous
16.64
synchronous
6 — 6 — 6 — tcyc
Input clock rise time t_SCKr
Input clock fall time t_SCKf
Input clock pulse width t_SCKw
— 1.5 — 1.5 — 1.5 tcyc
— 1.5 — 1.5 — 1.5 tcyc
0.4 0.6 0.4 0.6 0.4 0.6 tscy
c
Transmit data delay t_TXD
time
— 100 — 100 — 100 ns
Receive data setup t_RXS
time (synchronous)
100 — 100 — 100 — ns
Receive; Clock input t_RXH
data hold time (syn-
chronous);Clock _output
t_RXH
100 — 100 — 100 — ns
0 — 0 — 0 — ns
Port
Output data delay time t_PORTD — 20 — 17 — 15 ns
Input data setup time t_PORTS 20 — 15 — 12 — ns
Input data hold time t_PORTH 10 — 8 — 5 — ns
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