SH7708 Datasheet, PDF (152/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

BAMRB = H'02:
Address mask H'02
BBRB = H'0014:
Bus cycle, instruction fetch (pre-execution),
read (operand size not included in conditions)
BDRB = H'00000000: Data H'00000000
BDMRB = H'00000000: Data mask H'00000000
A user break is generated after execution of the instruction at address H'00000404 with ASID=
H'80, or before execution of instructions at addresses H'00008000 to H'000083FE with ASID =
H'70.
2. Instruction fetch cycle break condition setting (independent channel A and B conditions)
BRCR = H'0080: Channel A → channel B sequential conditions, pre-execution for channel A,
pre-execution for channel B
Channel A:
BASRA = H'80:
BARA = H'00037226:
BAMRA = H'00:
BBRA = H'0016:
ASID H'80
Address H'00037226
Address mask H'00
Bus cycle, instruction fetch (pre-execution),
read, word
Channel B:
BASRB = H'70:
ASID H'70
BARB = H'0003722E: Address H'0003722E
BAMRB = H'00:
Address mask H'00
BBRB = H'0016:
Bus cycle, instruction fetch (pre-execution),
read, word
BDRB = H'00000000: Data H'00000000
BDMRB = H'00000000: Data mask H'00000000
A user break is generated before execution of the instruction at address H'0003722E with ASID
= H'70, after execution of the instruction at address H'00037226 with ASID = H'80.
3. Data access cycle break condition setting
BRCR = H'0080: Independent channel A and B conditions, data break enable
Channel A:
BASRA = H'80:
BARA = H'00123456:
BAMRA = H'00:
BBRA = H'0024:
ASID H'80
Address H'00123456
Address mask H'00
Bus cycle, data access, read (operand size not
included in conditions)
Channel B:
138
BASRB = H'70:
ASID H'70
BARB = H'000ABCDE: Address H'000ABCDE
BAMRB = H'02:
Address mask H'02
BBRB = H'002A:
Bus cycle, data access, write, word
BDRB = H'0000A512: Data H'0000A512, (data break enable)
BDMRB = H'00000000: Data mask H'00000000