SH7708 Datasheet, PDF (281/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Refreshing: The bus state controller is provided with a function for controlling synchronous
DRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting
the RFSH bit to 1 in MCR. If synchronous DRAM is not accessed for a long period, self-refresh
mode, in which the power consumption for data retention is low, can be activated by setting both
the RMODE bit and the RFSH bit to 1.
1. Auto-Refreshing
Refreshing is performed at intervals determined by the input clock selected by bits CKS2–CKS0 in
RTCSR, and the value set in RTCOR. The value of bits CKS2–CKS0 in RTCOR should be set
so as to satisfy the refresh interval stipulation for the synchronous DRAM used. First make the
settings for RTCOR, RTCNT, and the RMODE and RFSH bits in MCR, then make the CKS2 to
CKS0 setting. When the clock is selected by CKS2–CKS0, RTCNT starts counting up from the
value at that time. The RTCNT value is constantly compared with the RTCOR value, and if the
two values are the same, a refresh request is generated and an auto-refresh is performed. At the same
time, RTCNT is cleared to zero and the count-up is restarted. Figure 10.28 shows the auto refresh
operation. Figure 10.29 shows the auto-refresh cycle timing.
First, an REF command is issued in the TRr cycle. After the TRr cycle, new command output
cannot be performed for the duration of the number of cycles specified by the TRAS bits in MCR
plus the number of cycles specified by the TPC bits in MCR. The TRAS and TPC bits must be
set to satisfy the synchronous DRAM refresh cycle time stipulation (active/active command delay
time).
Auto-refreshing is performed in normal operation, in sleep mode, and in a manual reset.
RTCOR value
RTCNT
RTCNT cleared to 0 when
RTCNT = RTCOR
H'00000000
RTCSR.CKS(2–0) = 000 ≠ 000
CMF
External bus
CMF flag cleared by start of
refresh cycle
Figure 10.28
Auto-refresh cycle
Auto-Refresh Operation
Time
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